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73k222au single-chip modem modem with uart april 2000 description the 73k222au is a compact, high-performance modem which includes a 8250a/16c450 compatible uart with the 1200 bit/s modem function on a single chip. based on the 73k222l 5v low power cmos modem ic, the 73k222au is the perfect modem/uart component for integral modem applications. it is ideal for applications such as portable terminals and laptop computers. the 73k222au is the first fully featured modem ic which can function as an intelligent modem in integral applications without requiring a separate dedicated microcontroller. it provides for data communication at 1200, 600, and 300 bit/s in a multi-mode manner that allows operation compatible with both bell 212a/103 and ccitt v.22/v.21 standards. the digital interface section contains a high speed version of the industry standard 8250a/16c450 uart, commonly used in personal computer products. a unique feature of the 73k222au is that the uart section can be used without the modem function, providing an additional asynchronous port at no added cost. the 73k222au is designed in cmos technology and operates from a single +5v supply. available packaging includes 40-pin dip or 44-pin plcc for surface mount applications. features ? modem/uart combination optimized for integral bus applications ? includes features of 73k222l single-chip modem ? fully compatible 16c450/8250 uart with 8250b or 8250a selectable interrupt emulation ? high speed uart will interface directly with high clock rate bus with no wait states ? single-port mode allows full modem and uart control from cpu bus, with no dedicated microprocessor required ? dual-port mode suits conventional designs using local microprocessor for transparent modem operation ? complete modem functions for 1200 bit/s (bell 212a, v.22) and 0-300 bit/s (bell 103, v.21) ? includes dtmf generator, carrier, call- progress and precise answer-tone detectors for intelligent dialing capability ? on chip 2-wire/4-wire hybrid driver and off- hook relay buffer ? speaker output with four-level software driven volume control ? low power cmos (40 mw) with power down mode (15 mw) ? operates from single +5v supply block diagram ud0 ud1 ud2 ud3 ud4 ud5 ud6 ud7 ua0 ua1 ua2 intrpt ( ) prst reset rxd int out1 vdd vref gnd iset stndln ( ) / ( ) / dclk / (n/c) / ( ) data / ( ) (ua3) / ma2 ( ) / ma1 ( ) / ma0 spkr rxa txa2 txa1 clk xtl2 xtl1 txd 1.8432 mhz internal data 8250a / 16c450 uart 73k222al 2w/4w hybrid 2 relay driver rxd-input oh
73k222au single-chip modem with uart 2 functional description the 73k222au integrates an industry standard 8250/16c450 uart function with the modem capability provided by the 73k222l single chip modem ic. the 73k222au is designed specifically for integral microprocessor bus intelligent modem products. these designs typically require the standard 8250 or higher speed 16450 uart to perform parallel-to-serial and serial-to-parallel conversion process necessary to interface a parallel bus with the inherently serial modem function. the 73k222au provides a highly integrated design which can eliminate multiple components in any integral bus modem application, and is ideal for internal pc modem applications. the 73k222au includes two possible operating modes. in the dual-port mode, the device is suitable for conventional plug-in modem card designs which use a separate local microprocessor for command interpretation and control of the modem function. in this mode, a dedicated microcontroller communicates with the 73k222au using a separate serial command port. in the single-port mode the main cpu can control both the uart and modem function using the parallel data bus. this allows very efficient modem design with no local microprocessor required for dedicated applications such as laptop pc?s or specialized terminals. to make designs more space efficient, the 73k222au includes the 2-wire to 4-wire hybrid drivers, off-hook relay driver, and an audio monitor output with software volume control for audible call progress monitoring. as an added feature the uart function can be used independent of the modem function, providing an added asynchronous port in a typical pc application with no additional circuitry required. uart function (16c450) the uart section of the 73k222au is completely compatible with the industry standard 16c450 and the 8250 uart devices. the bus interface is identical to the 16450, except that only a single polarity for the control signals is supported. the register contents and addresses are also the same as the 16c450. to insure compatibility with all existing releases of the 8250 uart design, external circuitry normally used in pc applications to emulate 8250b or 8250a interrupt operation has been included on the 73k222au. a select line is then provided to enable the desired interrupt operation. the uart used in the 73k222au can be used with faster bus read and write cycles than a conventional 16c450 uart. this allows it to interface directly with higher clock rate microprocessors with no need for external circuitry to generate wait states. the primary function of the uart is to perform parallel-to-serial conversion on data received from the cpu and serial-to-parallel conversion on data received from the internal modem or an external device. the uart can program the number of bits per character, parity bit generation and checking, and the number of stop bits. the uart also provides break generation and detection, detection of error conditions, and reporting of status at any time. a prioritized maskable interrupt is also provided. the uart block has a programmable baud rate generator which divides an internal 1.8432 mhz clock to generate a clock at 16 x the data rate. the data rate for the transmit and receive sections must be the same. for dpsk modulation, the data rate must be 1200 hz or 600 hz. for fsk modulation, the data rate must be 300 hz or less. the baud generator can create a clock that supports digital transfer at up to 115.2 khz. the output of the baud generator can be made available at the clk pin under program control. modem function (73k222al) the modem section of the 73k222au provides all necessary analog functions required to create a single chip bell 212a/103 and ccitt v.22/v.21 modem, controlled by the system cpu or a local dedicated microprocessor. asynchronous 1200 bit/s dpsk (bell 212a and v.22) and 300 baud fsk (bell 103 and v.21) modes are supported. the modem portion acts as a peripheral to the microprocessor. in both modes of operation, control information is stored in register memory at specific address locations. in the single-port mode, the modem section can be controlled through the 16c450 interface, with no external microcontroller required. the primary analog blocks are the dpsk modulator/demodulator, the fsk modulator/ demodulator, the high and low band filters, the agc, the special detect circuitry, and the dtmf tone generator. the analog functions are performed with switched capacitor technology.
73k222au single-chip modem with uart 3 psk modulator / demodulator the 73k222au modulates a serial bit stream into dibit pairs that are represented by four possible phase shifts as prescribed by the bell 212a or v.22 standard. the baseband signal is then filtered to reduce intersymbol interference on the band limited 2-wire pstn line. transmission occurs using either a 1200 hz (originate mode) or 2400 hz carrier (answer mode). demodulation is the reverse of the modulation process, with the incoming analog signal eventually decoded into dibits and converted back to a serial bit stream. the demodulator also recovers the clock which was encoded into the analog signal during modulation. the demodulator decodes either a 1200 hz carrier (originate carrier) or a 2400 hz carrier (answer carrier). the 73k222au uses a phase-locked-loop coherent demodulation technique that offers inherently better performance than typical dpsk demodulators used by other manufacturers. fsk modulator/demodulator the fsk modulator frequency modulates the analog output signal using two discrete frequencies to represent the binary data. in bell 103, the standard frequencies of 1270 hz and 1070 hz (originate mark and space) and 2225hz and 2025 hz (answer mark and space) are used. v.21 mode uses 980 hz and 1180 hz (originate, mark and space) or 1650 hz and 1850 hz (answer, mark and space). demodulation involves detecting the received frequencies and decoding them into the appropriate binary value. passband filters and equalizers a high and low band filter is included to shape the amplitude and phase response of the transmit signal and provide compromise delay equalization and rejection of out-of-band signals in the receive channel. amplitude and phase equalization is necessary to compensate for distortion of the transmission line and to reduce intersymbol interference in the band limited receive signal. the transmit signal filtering approximates a 75% square root of raised cosine frequency response characteristic. agc the automatic gain control maintains a signal level at the input to the demodulators which is constant to within 1 db. it corrects quickly for increases in signal which would cause clipping, and provides a total dynamic range of >45 db. special detect circuitry the special detect circuitry monitors the received analog signal to determine status or presence of carrier, call-progress tones, answer tone, and weak received signal (long loop condition). an unscrambled mark signal is also detected when the received data out of the dpsk demodulator before the descrambler has been high for 165.5 ms 13.5 ms. the appropriate status bit is set when one of these conditions changes and an interrupt is generated for all monitored conditions except long loop. the interrupts are disabled (masked) when the enable interrupt bit is set to a 0. dtmf generator the dtmf generator will output one of 16 standard dual-tones determined by a 4-bit binary value and tx dtmf mode bit previously loaded into the tone register. tone generation is initiated when the dtmf mode is selected and the transmit enable (cr0 bit d1) is changed from a 0 to a 1. test features test features such as analog loopback (alb), remote digital loopback, local digital loopback, and internal pattern generators are also included. line interface the line interface of the 73k222au consists of a two-to-four wire hybrid, and an off-hook relay driver. the two-to-four wire converter has a differential transmit output and requires only a line transformer and an external impedance matching resistor. four- wire operation is also available by simply using either of the transmit output signals. the relay driver output of the 73k222au is an open drain signal capable of sinking 20 ma, which can control a line closure relay used to take the line off hook and to perform pulse dialing. audio monitor an audio monitor output is provided which has a software programmable volume control. its output is the received signal. the audio monitor output can directly drive a high impedance load, but an external power amplifier is necessary to drive a low-impedance speaker.
73k222au single-chip modem with uart 4 pin description general name dip plcc type description vdd 40 44 i +5v supply 10%, bypass with a 0.1 and a 22 f capacitor to gnd gnd 20 22 i system ground vref 19 21 o vref is an internally generated reference voltage which is externally bypassed by a 0.1 f capacitor to the system ground. iset 9 11 i the analog current is set by connecting this pin to vdd through a 2 m ? resistor. iset should be bypassed to gnd. alternatively, an internal bias can be selected by connecting iset to gnd, which will result in a larger worst-case supply current due to the tolerance of on-chip resistors. bypass with 0.1 f capacitor if resistor is used. xtl1 xtl2 25 24 27 26 i i these pins are connections for the internal crystal oscillator requiring an 11.0592 mhz crystal. xtl2 can also be ttl driven from an external clock. connect a 10 m ? resistor from xtl1 to ground and a 1 m ? resistor from xtl1 to xtl2 clk 21 23 o output clock. this pin is selectable under processor control to be either the crystal frequency (which might be used as a processor clock) or the output of the baud generator. reset 10 12 i reset. an active signal (high) on this pin will put the chip into an inactive state. the control register bits (except the receiver buffer, transmitter holding, and divisor latches) will be reset. the output of the clk pin will be set to the crystal frequency. an internal pull-down resistor permits power-on reset using a 0.1 f capacitor connected to the 5v supply. stndln 15 17 i single-port mode select (active high). in a single-port system there is no local microprocessor and all the modem control is done through the 16c450 parallel bus interface. the local microprocessor interface is replaced with uart control signals which allow the device to function as a digital uart as well as modem.
73k222au single-chip modem with uart 5 uart interface name dip plcc type description ua2-ua0 ua3 37-39 12 41-43 14 i i uart address. these pins determine which of the uart registers is being selected during a read or write on the uart data bus. the contents of the dlab bit in the uart?s line control register also control which register is referenced. in single-port mode, ua0-ua3 are latched when ads goes high. in dual-port, only ua0-ua2 are used. udo-ud7 27-34 30-37 i/o (3 state) uart data. data or control information to the uart registers is carried over these lines. distr 35 38 i data input strobe. a low on this pin requests a read of the internal uart registers. data is output on the d0-d7 lines if distr and cs@ are active. dostr 36 39 i data output strobe. a low on this pin requests a write of the internal uart registers. data on the d0-d7 lines are latched on the rising edge of dostr . data is only written if both dostr and cs@ are active. cs@ 1 2 i chip select. a low on this pin allows a read or write to the uart registers to occur. in single port mode, cs@ is latched on ads . intrpt 5 7 o (3 state) uart interrupt. this signal indicates that an interrupt condition on the uart side has occurred. if the enable 8250a interrupt bit in the interrupt enable register is 0 the interrupt is gated by the distr signal to provide compatibility with the 8250b. the output can be put in a high impedance state with the out2 register bit in the modem control register. in single- port mode, intrpt also becomes valid when a modem interrupt signal is generated by the modem section?s detect register. function is determined by stndln pin and bit 7, tone control register: stndln d7 0 0 rxd outputs data received by modem. 1 0 rxd is electrically an input but signal is ignored. rxd 6 8 i/o x 1 rxd is a serial input to uart.
73k222au single-chip modem with uart 6 uart interface (continued) name dip plcc type description function is determined by stndln pin and bit 7, tone control register: stndln d7 0 0 txd is a serial output of uart. 1 0 txd is forced to a mark. txd 7 9 o x 1 txd is a serial output of uart. analog / line interface txa1 txa2 3 4 4 5 o o (differential) transmitted analog. these pins provide the analog output signals to be transmitted to the phone line. the drivers will differentially drive the impedance of the line transformer and the line matching resistor. an external hybrid can also be built using txa1 as a single ended transmit signal. rxa 16 18 i received analog. this pin inputs analog information that is being received by the two-to-four wire hybrid. this input can also be taken directly from an external hybrid. spkr 17 19 o speaker output. this pin outputs the received signal through a programmable attenuator stage, which can be used for volume control and disabling the speaker. oh 18 20 o off-hook relay driver. this signal is an open drain output capable of sinking 20 ma and is used for controlling a relay. the output is the complement of the oh register bit in cr3.
73k222au single-chip modem with uart 7 uart control interface (stndln = 1) (see figure 1: single-port mode) name dip plcc type description ads 23 25 i address strobe. ads is used to latch address and chip select to simplify interfacing to a multiplexed address/data bus. ua0- ua3 and cs@ are latched when the ads signal goes high. ua3 12 14 i uart address bit 3. ua3 is used in single-port mode to address the modem registers from the 16c450 interface. if ua3 is 0, the normal 16c450 registers are addressed by ua0-ua2 and if ua3 is 1, the modem registers are addressed. ua3 is latched when ads goes high. cts 14 16 i clear to send. this pin is the complement of cts bit in the modem status register. the signal is used in modem handshake control to signify that communications have been established and that data can be transmitted. dsr 13 15 i data set ready. this pin is the complement of dsr bit in the modem status register. the signal is used in modem handshake to signify that the modem is ready to establish communications. dcd 11 13 i data carrier detect. this pin is the complement of dcd bit in the modem status register. the signal is used in modem control handshake to signify that the modem is receiving a carrier. dtr 22 24 o data terminal ready. the dtr output is programmed through a bit in the modem control register. the signal is used in modem handshake to signify that the 16c450 is available to communicate. rts 23o request to send. the rts output is programmed through a bit in the modem control register. the signal is used in modem handshake to signify that the 16c450 has data to transmit. ri 810 i ring indicator. this indicates that a telephone ringing signal is being received. this pin is the complement of the ri bit in the modem status register.
73k222au single-chip modem with uart 8 pin description (continued) microprocessor interface (stndln = 0) (see figure 2: dual-port mode) name dip plcc type description ma0-ma2 12-14 14-16 i modem address control. these lines carry register addresses for the modem registers and should be valid throughout any read or write operation. data 22 24 i/o serial control data. serial control data to be read/written is clocked in/out on the falling edge of the dclk pin. the direction of data transfer is controlled by the state of the rd pin. if the rd pin is active (low) the data line is an output. conversely, if the rd pin is inactive (high) the data line is an input. rd 23 25 i read. a low on this input informs the 73k222au that control data or status information is being read by the processor from a modem register. wr 26 28 i write. a low on this input informs the 73k222au that control data or status information is available for writing into a modem register. the procedure for writing is to shift in data lsb first on the data pin for eight consecutive cycles of dclk and then to pulse wr low. data is written on the rising edge of wr . dclk 11 13 i data clock. the falling edge of this clock is used to strobe control data for the modem registers in or out on the data pin. the normal procedure for a write is to shift in data lsb first on the data pin for eight consecutive cycles of dclk and then to pulse wr low. data is written on the rising edge of wr . the falling edge of the rd signal must continue for eight cycles of dclk in order to read all eight bits of the reference register. read data is provided lsb first. data will not be output unless the rd signal is active. int 2 3 o (with weak pull-up) modem interrupt. this output signal is used to inform the modem processor that a change in a modem detect flag has occurred. the processor must then read the modem detect register to determine which detect triggered the interrupt. int will stay active until the processor reads the modem detect register or does a full reset. mprst* 810o microprocessor reset. this output signal is used to provide a hardware reset to the microprocessor. this signal is high if the reset pin is high or the mcr bit d3 (out1) bit is set. * note: the prst pin is an upgraded function which was not included in the initial definition of the 73k222au.
73k222au single-chip modem with uart 9 stndln = 1 modem control bits 1.8432 mhz baudout uart (8250) select logic +v digital loopback bus gateway two port scratch register baud generator (divisor latch ls) (divisor latch ms) transmitter (transmit holding register) receiver (receiver buffer register) interrupt logic (interrupt enable register) (interrupt id register) 16c450 uart control registers (line control register) (line status register) (modern control register) modem status register) n/c relay driver power modem control register (control register 0) (control register 1) (tone register) modem interrupt logic (detect register) additional control registers (control register 2) (uart control register) scrambler dpsk modulator fsk modulator dpsk modulator long loop detector carrier detector answer tone detector agc high band filter low band filter speaker gain control anti-alis lpf call progress detector analog loopback differential hybrid driver dtmf generator fsk modulator descrambler unscrambled mark (rdl) detector clock generator 1.8432 mhz vdd vref gnd iset xtal1 xtal2 clk spkr rxa txa1 txa2 rxd txd intrpt rst ua3 ua2 ua1 ua0 ud0-ud7 figure 1: single-port mode in the single-port mode, the 73k222au is designed to be accessed only by the main cpu using the same parallel bus utilized for data transfer. this mode is enabled when the stndln pin is at a logic ?1?. in the single port mode, internal registers are accessed by the main cpu to configure both the uart section and the modem function, eliminating the need for a separate microcontroller. in this mode, multiplexed pins provide the cts , dsr , dtr , ded and ri signals normally associated with the uart function. a separate pin, ads , is used for bus control.
73k222au single-chip modem with uart 10 stndln = 1 modem control bits 1.8432 mhz baudout out1 uart (8250) select logic digital loopback bus gateway two port scratch register baud generator (divisor latch ls) (divisor latch ms) transmitter (transmit holding register) receiver (receiver buffer register) interrupt logic (interrupt enable register) (interrupt id register) 16c450 uart control registers (line control register) (line status register) (modern control register) modem status register) ma1 ma0 ma2 data dclk relay driver power modem control register (control register 0) (control register 1) (tone register) modem interrupt logic (detect register) modem select logic and data shift register additional control registers (control register 2) (uart control register) scrambler dpsk modulator fsk modulator dpsk modulator long loop detector carrier detector answer tone detector agc high band filter low band filter speaker gain control anti-alis lpf call progress detector analog loopback differential hybrid driver dtmf generator fsk modulator descrambler unscrambled mark (rdl) detector clock generator 1.8432 mhz vdd vref gnd iset xtal1 xtal2 clk spkr rxa txa1 txa2 rxd txd prst rst ua3 ua2 ua1 ua0 ud0-ud7 figure 2: dual-port mode the dual-port mode allows use of a dedicated microprocessor for control of the modem function, and is enabled when the stndln pin = ?0?. this mode is useful for conventional plug-in card modem designs where it is necessary to make the modem function transparent to the main cpu. in this mode, the 73k222au?s multiplexed pins from the serial command bus used to communicate with the external microprocessor. the ri , cts , dsr , dtr , and dcd logic functions must then be implemented using ports the serial control interface allows access to the control and status registers via a serial command port. in this mode the ma0, ma1, and ma2 lines provide register addresses for data passed through the data pin under control of the rd and wr lines. a read operation is initiated when the rd line is taken low. the next eigh t cycles of dclk will then transfer out eight bits of the selected address location lsb first. a write takes place by shifting in eigh t bits of data lsb first for eight consecutive cycles of dclk. wr is then pulsed low and data transfer into the selected register occurs on the rising edge of wr .
73k222au single-chip modem with uart 11 uart control register overview register data bit number receiver buffer register (read only) transmit holding register (write only) interrupt enable register interrupt id register (read only) line control register modem control register line status register modem status register (read only) scratch register divisor latch (ls) divisor latch (ms) * in single-port mode (stndln pin = 1), all four address lines ua3-ua0 are used to address the uart control registers. * in dual-port mode (stndln pin = 0), only three address lines ua2-ua0 are used to address the uart control registers, the ua3 pin becomes the ma2 pin in this mode. rbr thr ier iir lcr mcr lsr msr scr dll dlm uart address ua3-ua0* 0000 dlab = 0 0000 dlab = 0 0001 dlab = 0 0000 dlab = 1 0001 dlab = 1 0010 0011 0100 0101 0110 0111 d7 bit 7 (msb) bit 7 (msb) 0 0 0 0 divisor latch access (dlab) data carrier detect (dcd) bit 7 bit 7 bit 15 d6 bit 6 bit 6 0 0 transmit shift reg empty (tsre) 0 set break ring indicator (ri) bit 6 bit 6 bit 14 d5 bit 5 bit 5 0 0 transmit holding register empty(thre) 0 stick parity data set ready (dsr) bit 5 bit 5 bit 13 d4 bit 4 bit 4 0 loop break interrupt (bi) enable 8250a/ 16c450 interrupt even parity select (eps) clear to send (cts) bit 4 bit 4 bit 12 d3 bit 3 bit 3 0 enable interrupt (out2 in 16c450) framing error (fe) enable modem status interrupt parity enable (pen) delta data carr. detect (ddcd) bit 3 bit 3 bit 11 d2 bit 2 bit 2 interrupt id bit 1 prst (out1 in 16c450) parity error (pe) enable rec. line status interrupt number of stop bits (stb) trailing edge ring indicator (teri) bit 2 bit 2 bit 10 d1 bit 1 bit 1 interrupt id bit 0 request to send (rts) overrun error (oe) enable thr empty interrupt word length select 1 (wls1) delta data set ready (ddsr) bit 1 bit 1 bit 9 d0 bit 0 bit 0 "0" if interrupt pending data terminal ready (dtr) data ready (dr) enable rec. data available interrupt word length select 0 (wls0) delta clear to send (dcts) bit 0 bit 0 bit 8
73k222au single-chip modem with uart 12 modem control register overview register control register 0 control register 1 detect register tone control register control register 2 control register 3 scratch register uart control register address stndln 01 ma2- ma0 ua3- ua0 cr0 cr1 dr tone cr2 cr3 scr ucr 000 001 010 011 100 101 110 111 1000 1001 1010 1011 1100 1101 1110 1111 d7 modulation option transmit pattern 1 device signature 1 rxd/txd control speaker volume 1 bit 7 txclk (read only) d6 0 transmit pattern 0 device signature 0 transmit guard tone speaker volume 0 bit 6 x d5 modulation mode enable detect interrupt receive data transmit answer tone off-hook bit 5 request to send (rts) (read only) d4 power on bypass scrambler unscr. mark detect transmit dtmf x bit 4 data term. ready (dtr) (read only) d3 character size 1 (read only) clk control carrier detect dtmf 3 x bit 3 ring indicator (ri) d2 character size 0 (read only) reset answer tone detect dtmf 2 x bit 2 data carrier detect (dcd) d1 transmit enable test mode 1 call progress detect dtmf 1 x bit 1 data set ready (dsr) d0 originate/ answer test mode 0 long loop detect dtmf 0 guard/ans. tone x bit 0 clear to send (cts) data bit number reserved for future use x = undefined, mask in software 0 = only write zero to this location
73k222au single-chip modem with uart 13 uart register bit descriptions receiver buffer register (rbr) (read only) stndln: 0 1 address: ua2 - ua0 = 000, dlab = 0 ua3 - ua0 = 0000, dlab = 0 this read only register contains the parallel received data with start, stop, and parity bits (if any) removed. the high order bits for less than 8 data bits/character will be set to 0. transmit holding register (thr) (write only) stndln: 0 1 address: ua2 - ua0 = 000, dlab = 0 ua3 - ua0 = 0000, dlab = 0 this write only register contains the parallel data to be transmitted. the data is sent lsb first with start, stop, and parity bits (if any) added to the serial bit stream as the data is transferred. interrupt enable register (ier) stndln: 0 1 address: ua2 - ua0 = 001, dlab = 0 ua3 - ua0 = 0001, dlab = 0 this 8-bit register enables the four types of interrupts of the uart to separately activate the chip interrupt (intrpt) output signal. it is possible to totally disable the interrupt system by resetting bits 0 through 3 of the interrupt enable register. similarly, by setting the appropriate bits of this register to a logic 1, selected interrupts can be enabled. disabling the interrupt system inhibits the interrupt identification register and the active (high) intrpt output from the chip. all other system functions operate in their normal manner, including the setting of the line status and modem status registers. bit no. name condition description d0 received data 1 this bit enables the received data available interrupt when set to logic 1. d1 transmitter holding register empty 1 this bit enables the transmitter holding register empty interrupt, when set to logic 1. d2 receiver line status interrupt 1 this bit enables the receiver line status interrupt, when set to logic 1. d3 modem status 1 this bit enables the modem status register interrupt when set to interrupt logic 1. d4 8250a/16450 1/0 set for compatibility with 8250a/16c450 uarts. reset this bit to disable the gating of the intrpt interrupt line with the distr signal which is needed for 8250b compatibility. d5 - d7 not used 0 these three bits are always logic 0. uart section
73k222au single-chip modem with uart 14 interrupt id register (iir) (read only) stndln: 0 1 address: ua2 - ua0 = 010 ua3 - ua0 = 0010 the iir register gives prioritized information as to the status of interrupt conditions. when accessed, the iir freezes the highest priority interrupt pending and no other interrupts are acknowledged until the particular interrupt is serviced by the cpu. bit no. name condition description this bit can be used in either a hardwired priortized or polled environment to indicate whether an interrupt is pending. when bit 0 is a logic 0, an interrupt is pending and the iir contents may be used as a pointer to the appropriate interrupt service routine. d0 interrupt pending 0 1 when bit 0 is a logic 1, no interrupt is pending. d1, d2 interrupt id bits 0, 1 table below these two bits of the iir are used to identify the highest priority interrupt pending as indicated in the following table. d3 - d7 not used 0 these five bits of the iir are always logic 0. interrupt priority table d2 d1 d0 priority type source reset 0 0 1 - none none - 1 1 0 highest receiver line status overrun error, parity error, framing error or break interrupt reading the line status register 1 0 0 second receive data available receive data available reading the rcvr. buffer register 0 1 0 third transmit holding register empty transmit holding register empty reading iir register (if source of interrupt) or writing to transmit holding register 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier det. reading the modem status register uart section
73k222au single-chip modem with uart 15 line control register (lcr) stndln: 0 1 address: ua2 - ua0 = 011 ua3 - ua0 = 0011 the user specifies the format of the asynchronous data communications exchange via the line control register. in addition to controlling the format, the user may retrieve the contents of the line control register for inspection. this feature simplifies system programming and eliminates the need for separate storage in system memory of the line characteristics. bit no. name condition description bits d0 and d1 select the number of data bits per character as shown: d1 d0 word length 0 0 5 bits 0 1 6 bits 1 0 7 bits d0 d1 word length select 0 word length select 1 1 1 8 bits d2 number of stop bits 0 or 1 this bit specifies the number of stop bits in each transmitted character. if bit 2 is a logic 0, one stop bit is generated in the transmitted data. if bit 2 is a logic 1 when a 5-bit word length is selected via bits 0 and 1, one-and-a-half stop bits are generated. if bit 2 is a logic 1 when either a 6, 7, or 8-bit word length is selected, two stop bits are generated. the receiver checks the first stop bit only, regardless of the number of stop bits selected. d3 parity enable 1 this bit is the parity enable bit. when bit 3 is a logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd number of 1?s when the data word bits and the parity bit are summed). d4 even parity select 1 or 0 this bit is the even parity select bit. when bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of logic 1?s are transmitted or checked in the data word bits and parity bit. when bit 3 is a logic 1 and bit 4 is a logic 1, an even number of logic 1?s are transmitted or checked. uart section
73k222au single-chip modem with uart 16 line control register (lcr) (continued) bit no. name condition description 1 or 0 this bit is the stick parity bit. when bit 3 is a logic 1 and bit 5 is a logic 1, the parity bit is transmitted and checked by the receiver as a logic 0 if bit 4 is a logic 1 or as a logic 1 if bit 4 is a logic 0. d5 d4 parity 0 0 odd parity 0 1 even parity 10mark parity d5 stick parity 1 1 space parity d6 set break 1 output of modem is set to a spacing state. when the modem is transmitting dpsk data if the set break bit is held for one full character (start, data, parity, stop) the break will be extended to 2 n + 3 space bits (where n = # data bits + parity bit + 1 start + 1 stop). any data bits generated during this time will be ignored. see note below. d7 divisor latch access bit (dlab) 1 this bit is the divisor latch access bit (dlab). it must be set high (logic 1) to access the divisor latches of the baud generator during a read or write operation. it must be set low (logic 0) to access the receiver buffer, the transmitter holding register, or the interrupt enable register. note: this feature enables the cpu to alert a terminal in a computer communications system. if the following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break. 1. load an all 0?s pad character in response to thre. 2. set break in response to the next thre. 3. wait for the transmitter to be idle. (tsre = 1), and clear break when normal transmission has to be restored. during the break, the transmitter can be used as a character timer to accurately establish the break duration. uart section
73k222au single-chip modem with uart 17 modem control register (mcr) stndln: 0 1 address: ua2 - ua0 = 100 ua3 - ua0 = 0100 the mcr register controls the interface with the modem. bits d1 and d0 are also available as read only bits in the uart control register in the modem registers. in single-port mode, bits d1 and d0 are available inverted at the rts and dtr pins. bit no. name condition description d0 dtr 1 this bit controls the data terminal ready ( dtr ) output. when bit 0 is set to a logic 1, the dtr output is forced to a logic 0. when bit 0 is reset to a logic 0, the dtr output is forced to a logic 1. d1 rts 1 this bit controls the request to send ( rts ) output. when bit 1 is set to a logic 1, the rts output is forced to a logic 0. when bit 1 is reset to a logic 0, the rts output is forced to a logic 1. d2 prst* (out1 in 16c450) 1 in single-port mode inactive unless loop = 1, then functions as below (d4). in dual-port mode the prst pin is the logical or of this bit and the reset pin. 0 sets intrpt pin to high impedance if stndln = 1. d3 enable interrupt (out2 in 16c450) 1 intrpt output enabled. d4 loop 1 this bit provides a local loopback feature for diagnostic testing of the uart portion of the 73k222au. when bit d4 is set to logic 1, the following occurs: 1. txd is forced to mark, rxd is ignored. 2. the output of the transmitter is looped to the receiver. 3. the four modem control inputs to the uart ( cts , dsr , dcd , and ri ) are ignored and the uart signals rts , dtr , enable interrupt, and prst are forced inactive. 4. the uart signals rts, dtr, enable interrupt, and prst are internally connected to the four control signals cts, dsr, dcd and ri respectively. note that the modem status register interrupts are now controlled by the lower four bits of the modem control register. the interrupts are still controlled by the interrupt enable register. d5 - d7 0 these bits are permanently set to logic 0. * note: the prst bit has an upgraded function which was not included in the initial definition of the 73k222au. uart section
73k222au single-chip modem with uart 18 line status register (lsr) stndln: 0 1 address: ua2 - ua0 = 101 ua3 - ua0 = 0101 this register provides status information to the cpu concerning the data transfer. bit no. name condition description d0 dr 1 the data ready (dr) bit is set to a 1 whenever a complete incoming character has been received and transferred into the receiver buffer register. data ready is reset to 0 by reading the data in the receiver buffer register or by writing a 0 into it from the processor. d1 oe 1 the overrun error (oe) bit indicates that the data in the receiver buffer register was not read by the cpu before the next character was transferred into the receiver buffer register, thereby destroying the previous character. the oe indicator is reset whenever the cpu reads the contents of the line status register. d2 pe 1 the parity error (pe) bit indicates that the received character did not have the correct parity. the bit is reset to 0 whenever the cpu reads the line status register. d3 fe 1 the framing error (fe) bit indicates that the received character did not have a valid stop bit. the fe indicator is reset whenever the cpu reads the contents of the line status register. a framing error will not occur in dpsk receive from the modem due to the fact that missing stop bits are reinserted. d4 bi 1 the break interrupt (bi) bit indicates that a break has been received. a break occurs whenever the received data is held to 0 for a full data word (start + data + stop) or for two full data words when receiving in dpsk mode from the modem. the bi bit is reset to 0 whenever the cpu reads the line status register. d5 thre 1 the transmit holding register empty (thre) indicates that the transmitter is ready to accept a new character for transmission. the thre bit is reset when the cpu loads a character into the transmit holding register. d6 tsre 1 the transmit shift empty (tsre) indicates that both the transmit holding register and the transmit shift registers are empty. d7 - 0 always zero. uart section
73k222au single-chip modem with uart 19 modem status register (msr) (read only) stndln: 0 1 address: ua2 - ua0 = 110 ua3 - ua0 = 0110 this register provides the current state of the control signals from the modem. in addition, four bits provide change information. the cts, dsr, dcd, and ri signals come from the uart control register if stndln = 0 and from the cts , dsr , dcd and ri pins (inverted) if stndln = 1. this register is read only. the delta bits indicate whether the inputs have changed since the last time the modem status register has been read. in loop mode cts, dsr, ri and dcd are taken from rts, dtr, prst, and enable interrupt in the modem control register respectively. bit no. name condition description d0 dcts 1 this bit is the delta clear to send (dcts) indicator. bit 0 indicates that the cts input to the chip has changed state since the last time it was read by the cpu. d1 ddsr 1 this bit is the delta data set ready (ddsr) indicator. bit 1 indicates that the dsr input to the chip has changed state since the last time it was read by the cpu. d2 teri 1 this bit is the trailing edge of the ring indicator (teri) detector. bit 2 indicates that the ri input to the chip has changed state. d3 ddcd 1 this bit is the delta data carrier detect (ddcd) indicator. bit 3 indicates that the dcd input to the chip has changed state. d4 cts 1 this bit is the complement of the clear to send ( cts ) input. if stndln = 0, this reflects the status of the uart control register bit. if bit 4 (loop) of the mcr is set to a 1, this bit is equivalent to rts in the mcr. d5 dsr 1 this bit is the complement of the data set ready ( dsr ) input. if stndln = 0, this reflects the status of the uart control register bit. if bit 4 of the mcr is set to a 1, this bit is the equivalent of dtr in the mcr. d6 ri 1 this bit is the complement of the ring indicator ( ri ) input. if stndln = 0, this reflects the status of the uart control register bit. if bit 4 of the mcr is set to a 1, this bit is equivalent to prst in the mcr. d7 dcd 1 this bit is the complement of the data carrier detect ( dcd ) if stndln = 0, this reflects the status of the uart control register bit. if bit 4 of the mcr is set to a 1, this bit is equivalent to enable interrupt in the mcr. uart section
73k222au single-chip modem with uart 20 scratch register (scr) stndln: 0 1 address: ua2 - ua0 = 111 ua3 - ua0 = 0111 the scratch register is a dual port register which can be simultaneously accessed through both the uart bus and the modem bus. this provides the possibility for the modem controller to communicate directly with the central cpu. note that if both processors write the scratch register, the data stored will be from whichever processor last wrote the register. divisor latch (least significant byte) (dll) stndln: 0 1 address: ua2 - ua0 = 000, dlab = 1 ua3 - ua0 = 0000, dlab = 1 divisor latch (most significant byte) (dlm) stndln: 0 1 address: ua2 - ua0 = 001, dlab = 1 ua3 - ua0 = 0001, dlab = 1 divisor latch value vs. data rate the divisor latch is two 8-bit write only registers which control the rate of the programmable baud generator. the programmable baud generator generates an output clock by dividing an internal 1.8432 mhz clock by the value stored in the divisor latch. this output clock has a value of 16x the data rate at which the modem will operate. this output clock is available at pin 21 under the control of bit 3 (d3) of the modem control register 1. upon loading either of the divisor latches the 16-bit device counter is immediately loaded, preventing long counts on initial load. the following table shows divisor values for common data rates. desired data rate divisor used for 16 x data rate clock % error generated desired data rate divisor used for 16 x data rate clock % error generated 50 1 2304 4800 24 75 1 1536 7200 16 110 1 1047 9600 12 134.5 1 857 0.058 19200 6 159 1 768 38400 3 300 1 384 56000 2 2.86 600 2 192 1200 3 96 1800 64 2000 58 0.69 2400 48 3600 32 1. data rate valid for fsk transmission. 2. data rate valid for halfspeed dpsk transmission. 3. data rate valid for normal 1200 bit/s dpsk transmission. uart section
73k222au single-chip modem with uart 21 modem register bit descriptions control register (cr0) stndln: 0 1 address: ma2 - ma0 = 000 ua3 - ua0 = 1000 bit no. name condition description selects answer mode (transmit in high band, receive in low band). selects originate mode (transmit in low band, receive in high band). d0 d1 answer/originate transmit enable 0 1 0 disables transmit output at txa. 1 enables transmit output at txa. note: answer tone and dtmf tx control require transmit enable. if transmit enable is on, call progress and answer tone detector interrupts are masked. these bits are read only. these bits represent the character size. the character size is determined by the uart line control register and includes data, parity (if used), one start bit, and one stop bit. d3 d2 character length 0 0 8-bit character 0 1 9-bit character 1 0 10-bit character d2, d3 character size 0, 1 1 1 11-bit character d4 power on this bit controls the power down mode of the 73k222au, the analog, and most digital portions of the chip. the digital interface is active during power down. 0 power down mode. 1 normal operation. 0dpsk d5 modulation mode 1fsk d6 reserved 0 must be written as zero. d7 modulation option 0 dpsk: 1200 bit/s 1 600 bit/s 0 fsk: 103 mode 1 v.21 mode modem section
73k222au single-chip modem with uart 22 control register (cr1) stndln: 0 1 address: ma2 - ma0 = 001 ua3 - ua0 = 1001 bit no. name condition description d1 d0 0 0 selects normal operating mode. 0 1 analog loopback mode. loops the transmitted analog signal back to the receiver, and causes the receiver to use the same center frequency as the transmitter. to squelch the txa pin, transmit enable bit must be forced low. 1 0 selects remote digital loopback. received data is looped back to transmit data internally, and rxd is forced to a mark. data in txd is ignored. d0, d1 test mode 1 1 selects half-duplex. internally performs a logical and of txd and rxd to send to the uart receiver. both transmit and receive characters will occur at the receiver buffer register. 0 selects normal operation. d2 reset 1 resets modem to power down state. all control register bits (cr0, cr1, tone) are reset to zero. the output of the clock pin will be set to the crystal frequency. 0 clk pin output is selected to be an 11.0592 mhz crystal echo output. d3 clk control (clock control) 1 clk pin output is selected to be 16 x the data rate set by the uart divisor latch. 0 selects normal operation. dpsk data is passed through scrambler. d4 bypass scrambler 1 selects scrambler bypass. dpsk data is routed around scrambler in the transmit path. modem section
73k222au single-chip modem with uart 23 control register (cr1) (continued) bit no. name condition description 0 disables interrupts generated by detect register bits d1 - d4 at int pin in dual-port mode, or at intrpt pin in single-port mode. all interrupts normally disabled in power down modes. d5 enable detect interrupt 1 enables interrupts generated by detect register bits d1 - d4 at int pin in dual-port mode, or at intrpt pin in single-port mode. an interrupt will be generated with a change in status of dr bits d1 - d4. the answer tone and call progress detect interrupts are masked when the tx enable bit is set. carrier detect is masked when tx dtmf is activated. all interrupts will be disabled if the device is in power down mode. the interrupt is reset when the dr register is read. d7 d6 0 0 selects normal data transmission as controlled by the state of the txd pin. 0 1 selects an alternating mark/space transmit pattern for modem testing. 1 0 selects a constant mark transmit pattern. d6, d7 transmit pattern 1 1 selects a constant space transmit pattern. modem section
73k222au single-chip modem with uart 24 detect register (dr) stndln: 0 1 address: ma2 - ma0 = 010 ua3 - ua0 = 1010 bit no. name condition description 0 indicates normal received signal. d0 long loop 1 indicates low received signal level (< -38 dbm). 0 no call progress tone detected. d1 call progress detect 1 indicates presence of call progress tones. the call progress detection circuitry is activated by energy in the normal 350 to 620 hz call progress bandwidth. 0 no answer tone detected. d2 answer tone received 1 indicates detection of 2225 hz answer tone in bell mode or 2100 hz in ccitt mode. the device must be in originate mode for detection of answer tone for normal operation. for ccitt answer tone detection, bit d0 of the tone register must be set. 0 no carrier detected in the receive channel. d3 carrier detect 1 carrier has been detected in the receive channel. 0 no unscrambled mark detected. d4 unscrambled marks 1 indicates detection of unscrambled marks in the received data. a valid indication requires that unscrambled marks be received for > 165.5 13.5 ms. d5 receive data continuously outputs the received data stream. this data is the same as that output on the rxd pin, but it is not disabled when rxd is tri-stated. d7 d6 product identified 0 0 73k212u (special order only) 0 1 73k221u (special order only) d6, d7 device signature 0, 1 1 0 73k222au modem section
73k222au single-chip modem with uart 25 tone control register (tone) stndln: 0 1 address: ma2 - ma0 = 011 ua3 - ua0 = 1011 the tone control register contains information on the tones that are transmitted. tones are transmitted only if the transmit enable bit is set. the priority of the transmit tones are: 1) dtmf, 2) answer, 3) fsk, 4) guard. bit no. name condition description d6 d5 d4 d0 d0 interacts with bits d6, d5, and d4 as shown: x x 1 x transmit dtmf tones. x 1 0 0 select 2225 hz answer tone (bell). x 1 0 1 select 2100 hz answer tone (ccitt). 1 0 0 0 select 1800 hz guard tone. d0 dtmf 0 / answer/ guard tone 1 0 0 1 select 550 hz guard tone. d0, d1, d2, d3 dtmf table below: programs 1 of 16 dtmf tone pairs that will be transmitted when tx dtmf and tx enable bit (cr0, bit d1) is set. tone encoding is shown below. keyboard equivalent dtmf code d3 d2 d1 d0 tones low high 1 0 0 0 1 697 1209 2 0 0 1 0 697 1336 3 0 0 1 1 697 1477 4 0 1 0 0 770 1209 5 0 1 0 1 770 1336 6 0 1 1 0 770 1477 7 0 1 1 1 852 1209 8 1 0 0 0 852 1336 9 1 0 0 1 852 1477 0 1 0 1 0 941 1336 * 1 0 1 1 941 1209 # 1 1 0 0 941 1477 a 1 1 0 1 697 1633 b 1 1 1 0 770 1633 c 1 1 1 1 852 1633 d 0 0 0 0 941 1633 modem section
73k222au single-chip modem with uart 26 tone control register (tone) (continued) bit no. name condition description 0 disable dtmf. d4 tx dtmf (transmit dtmf) 1 activates dtmf. the selected dtmf tones are transmitted continuously when this bit is high. tx dtmf overrides all other transmit functions. d5 d0 d5 interacts with bit d0 as shown. 0 x disables answer tone generator. 1 0 enables answer tone generator. a 2225 hz answer tone will be transmitted continuously when the transmit enable bit is set. the device must be in answer mode. d5 tx ans (transmit answer tone) 1 1 enables a 2100hz answer tone generator, with operation same as above. 0 disables guard tone generator. d6 tx guard (transmit guard tone) 1 enables guard tone generator. (see d0 for selection of guard tones). stndln d7 function is dependant on status of stndln pin. 0 0 rxd is output data received by modem, txd is serial output of uart. for monitoring only. 10 rxd is electrically an input, but the signal is ignored, txd is forced to a mark. d7 rxd/txd control 1 1 rxd is serial input to uart, txd is serial output of uart. control register (cr3) stndln: 0 1 address: ma2 - ma0 = 101 ua3 - ua0 = 1101 d0 - d4 not used not presently used. 0 relay driver open. d5 off hook 1 open drain driver pulling low. d7 d6 speaker volume control status. 00speaker off 0 1 -24 db 1 0 -12 db d6, d7 speaker volume 0, 1 1 1 0 db modem section
73k222au single-chip modem with uart 27 scratch register (scr) stndln: 0 1 address: ma2 - ma0 = 110 ua3 - ua0 = 1110 the scratch register is a dual-port register which can be accessed either through the uart bus or the modem bus. it can be used for a communication path outside the data stream. uart control register (ucr) stndln: 0 1 address: ma2 - ma0 = 111 ua3 - ua0 = 1111 the uart control register contains the handshaking signals necessary for the microprocessor to communicate with the central cpu through the uart. bit no. name condition description d0 d1 d2 d3 cts dsr dcd ri 1 1 1 1 in dual-port mode, cts, dsr, dcd and ri are writeable locations which can be read through the 16c450 port in the modem status register. in the single-port mode, d0 - d3 are ignored and the information for the modem status register comes directly from the external pins. d4 d5 dtr rts 1 1 dtr and rts are read only versions of the same register bits in the modem control register. d6 not used d7 txclk clock txclk is the clock that the uart puts out with txd. the falling edge of txclk is coincident with the transitions of data on txd. txclk can also be used for the microprocessor to send synchronous data independent of the uart by forcing data patterns using cr1 bits 6 and 7 before the rising edge of txclk. note: control register 2 (cr2) is reserved for future products and is disabled. modem section
73k222au single-chip modem with uart 28 electrical specifications absolute maximum ratings ta = -40 c to 85 c, vdd = 5v 10%, unless otherwise noted. parameter rating unit vdd supply voltage 7 v storage temperature -65 to 150 c soldering temperature (10 sec.) 260 c applied voltage -0.3 to vdd +0.3 v note: all inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-circuit protected. recommended operating conditions parameter condition min nom max unit vdd, supply voltage 4.5 5 5.5 v ta, operating free-air temperature -40 85 c external component (refer to application drawing for placement.) vref bypass capacitor 2 (vref to gnd) 0.1 f bias setting resistor 1 (placed between vdd and iset pins) 1.8 2 2.2 m ? iset bypass capacitor 2 iset pin to gnd 0.1 f vdd bypass capacitor 2 (vdd to gnd) 0.1 f xtl1 load capacitor from pin to gnd 40 pf xtl2 load capacitor from pin to gnd 20 pf input clock variation (11.0592 mhz) -0.01 +0.01 % hybrid loading r1 see figure 3 600 ? r2 600 ? c txa hybrid loading 0.033 f 1. optional for minimum worst case current consumption. 2. minimum for optimized system layout; may require higher values for noisy environments.
73k222au single-chip modem with uart 29 dc electrical characteristics ta = -40 c to +85 c, vdd = 5v 10%, unless otherwise noted. parameter condition min nom max unit idd, supply current idda, active iset resistor = 2 m ? 812ma idda, active iset = gnd 8 15 ma idd1, power-down clk = 11.0592 mhz 3 4 ma idd2, power-down clk = 19.200 khz 2 3 ma digital inputs input high current iih vi = vdd 100 a input low current iil vi = 0 -200 a input low voltage vil 0.8 v input high voltage vih except reset & xtl1 2.0 v input high voltage vih reset & xtl1 3.0 v pull down current reset pin 530a input capacitance 10 pf digital outputs output high voltage voh iout = - 1 ma 2.4 vdd v vol ud0-ud7 and intrpt iout = 3.2 ma 0.4 v vol other outputs iout = 1.6 ma 0.4 v clk output vol iout = 3.2 ma 0.6 v oh output vol iout = 20 ma 1.0 v oh output vol iout = 10 ma 0.5 v offstate current intrpt pin vo = 0v -20 20 a capacitance inputs input capacitance 10 pf clk maximum capacitive load to pin 15 pf analog pins rxa input resistance 200 k ? rxa input capacitance 25 pf
73k222au single-chip modem with uart 30 electrical specifications (continued) dynamic characteristics and timing ta = -40 c to +85 c, vdd = 5v 10%, unless otherwise noted. parameter condition min nom max unit dpsk modulator carrier suppression measured at txa 55 db ans tone 2225 or 2100 hz -11 -10.0 -9 dbm0 dpsk tx scrambled marks -11 -10.0 -9 dbm0 output amplitude fsk dotting pattern -11 -10.0 -9 dbm0 fsk tone error bell 103 or v.21 5 hz dtmf generator freq. accuracy -.25 .25 % output amplitude low band, not in v.21 mode -10 -9 -8 dbm0 output amplitude high band, not in v.21 mode -8 -7 -6 dbm0 long loop detect dpsk or fsk -40 -32 dbm0 demodulator dynamic range dpsk or fsk 45 db call progress detector detect level 2-tones in 350-600 hz band -39 0 dbm0 reject level 2-tones in 350-600 hz band -46 dbm0 delay time -70 dbm0 to -30 dbm0 step 27 80 ms hold time -30 dbm0 to -70 dbm0 step 27 80 ms hysteresis 2 db carrier detect threshold dpsk or fsk receive data -49 -42 dbm0 delay time -70 dbm0 to -30 dbm0 step 15 45 ms hysteresis 2 3.0 db hold time -30 dbm0 to -70 dbm0 step 10 24 ms answer tone detector detect level threshold in fsk mode -49.5 -42 dbm0 delay time -70 dbm0 to -30 dbm0 step 20 45 ms hold time -30 dbm0 to -70 dbm0 step 10 30 ms detect frequency range -2.5 +2.5 % 1. all units in dbm0 are measured at the line input to the transformer. the interface circuit inserts an 8 db loss in the transmit path (txa1 - txa2 to line), and a 3 db loss in the receive path (line to rxa).
73k222au single-chip modem with uart 31 dynamic characteristics and timing (continued) parameter condition min nom max unit speaker output gain error -1 +1 db output swing spkr 10k||50 pf load 5% thd 2.75 vp carrier vco capture range originate or answer -10 10 hz capture time -10 hz to +10 hz carrier frequency change assumed 40 100 ms recovered clock capture range % of center frequency -625 +625 ppm data delay time analog data in at rxa pin to receive data valid at rxd pin. 30 50 ms guard tone generator tone accuracy 550 or 1800 hz -20 +20 hz tone level (below dpsk output) 550 hz 1800 hz -4.0 -7.0 -3.0 -6.0 -2.0 -5.0 db db harmonic distortion 700 to 2900 hz -60 db serial bus interface (see figure 4) the following times are for cl = 100 pf. parameter min nom max unit data out from read 70 ns data out after clock 110 ns data float after read 40 ns clock high after read 0 ns write width 65 10000 ns data setup before clock 0 ns data hold after clock 55 ns write after clock 60 ns address setup before control 1 0ns address hold after control 1 100 ns address setup before write low 0 ns address hold after write high 0 ns 1. control is later of falling edge of rd or dclk.
73k222au single-chip modem with uart 32 electrical specifications (continued) parallel bus interface (see figure 5) the following times are for ci = 100 pf. parameter min max min max unit dual-port mode single-port mode rc read cycle = tad + trc 240 340 ns tdiw distr width 30 30 ns tddd delay distr to data (read time) 45 45 ns thz** distr to floating data delay 50 40 ns tra address hold after distr 20 5 ns trcs chip select hold after distr 20 20 ns tar* distr delay after address 22 15 ns tcsr distr delay after chip select 20 20 ns wc write cycle = taw + tdow + twc 140 140 ns tdow dostr width 40 40 ns tds data setup 15 25 ns tdh** data hold 5 5 ns twa address hold after dostr 20 5 ns twcs chip select hold after dostr 20 20 ns taw* dostr delay after address 0 15 ns dostr delay after chip select 20 20 ns tads address strobe width 15 ns tas address setup time 10 ns tah address hold time 0 ns tcs chip select setup time 10 ns tch chip select hold time 0 ns trc read cycle delay 40 40 ns twc write cycle delay 40 40 ns tad address to read data 110 110 ns * tar and taw are referenced from the falling edge of either cs@ or distr or dostr , whichever is later. ** thz and tdh are referenced from the rising edge of cs@ or distr or dostr , whichever is earlier.
73k222au single-chip modem with uart 33 figure 3: txa hybrid loading analog interface hybrid loading figure 4: modem serial bus timing r1 600 r2 1:1 c txa1 (nominal telephone line impedance) ta hybrid loading analog interface hybrid loading rxa txa2 read mode write mode dclk trck trd tcar 1 tcar 1 tac r 1 tac r 1 addr addr tww tckw tac w tcaw tckh d0 d0 d1 d2 d6 d7 d1 tckd trdf d6 d7 address data dclk address data tdck
73k222au single-chip modem with uart 34 figure 5: uart bus timing (stndln = 1) address ua2 (ua3)-ua0 data ud7-ud0 read data write data low for no valid for no low for no valid for no valid valid tads ta s ta s ta h tch tcs ta r ta r tddd thz tds tdh ta d tdiw tra tcs taw tcsw taw rc tdow or wc twa tch trc taw twc ta h
73k222au single-chip modem with uart 35 typical performance characteristics the 73k222au was designed using an integrated analog/digital architecture that offers optimum performance over a wide range of line conditions. the 73k222au utilizes the circuit design proven in tdk semiconductor?s 73k222l one-chip modem, with added enhancements which extend low signal level performance and increase immunity to spurious noise typically encountered in integral bus applications. the 73k222au provides excellent immunity to the types of disturbances present with usage of the dial-up telephone network. the following curves show representative bit error rate performance under various line conditions. ber vs. s/n this test measures the ability of the modem to function with minimum errors when operating over noisy lines. since some noise is generated by even the best dial-up lines, the modem must operate with as low a s/n ratio as possible. optimum performance is shown by curves that are closest to the zero axis. a narrow spread between curves for the four line conditions indicates minimal variation in performance when operating over a range of line qualities and is typical of high performance adaptive equalization receivers. high band receive data is typically better than low band due to the inherent design of psk modems. 600 bps 1200 bps high band receive -30 dbm dpsk operation c2 c2 flat flat c1 or 3002 c1 or 3002 10 -2 10 -2 10 -3 10 -4 10 -5 10 -6 10 -3 10 -4 10 -5 10 -6 2 4 6 8 10 12 14 10 0 -10 -20 -30 -40 -50 bit error rate bit error rate signal to noise (db) receive level (dbm) 73k222au ber vs s/n 73k222au ber vs receive level high band receive dpsk operation c2 line s/n = 10.8 db s/n = 15 db
73k222au single-chip modem with uart 36 ber vs. receive level this measures the dynamic range of the modem. as signal levels vary widely over dial-up lines, the widest dynamic range possible is desirable. the minimum bell specification calls for 36 db of dynamic range. s/n ratios were held constant at the indicated values while receive level was lowered from very high to very low signal levels. the ?width of the bowl? of these curves taken at the 10 -4 ber point is a measure of the dynamic range. ber vs. carrier offset this parameter indicates how the modem performance is impacted by frequency shifts encountered in normal pstn operation. flat curves show no performance degradation from frequency offsets. the k-series devices use a 2nd order carrier tracking phase-locked-loop, which is insensitive to carrier offsets in excess of 10 hz. the bell network specifications allow as much as 7 hz offset, and the ccitt specifications require modems to operate with 7 hz of offset. application the 73k222au includes additional circuitry to greatly simplify integral modem designs in either of two different configurations. the single-port mode represents the most efficient implementation for an integral modem. figure 9 shows a typical schematic using this mode. in this configuration, the 73k222au transfers data and commands through the single parallel port. all modem control is provided by the main cpu, eliminating the need for an external microcontroller and supporting components. the 73k222au is unique in that access to both the uart and modem sections is possible through the uart port. also shown is a separate serial port, which can be used independent of the modem function when the modem section is inactive. figure 10 shows a more conventional integral modem design, in which a local microprocessor handles modem supervision, allowing the modem function to be transparent to the main processor. inclusion of the hybrid drivers, audio volume control, and off hook relay driver reduces component count for a highly efficient design. in either mode of operation, the 73k222au?s ability to operate from a single +5 volt power supply eliminates the need for additional supply voltages and keeps power usage to a minimum. (see figure 9 & 10: typical integral applications single and dual-port modes.) c2 10.8 db s/n 3002 11.5 db s/n high band receive dpsk operation 10 -2 10 -3 10 -4 10 -5 10 -6 12 8 4 0 -4 -8 -12 bit error rate signal to noise (db) 73k222au ber vs carrier offset
73k222au single-chip modem with uart 37 pc bus u2 optional digital serial port 73k222au line phone irq a0 a31 a1 a30 a2 a29 a3 a28 a4 a27 a5 a26 a6 a25 a7 a24 a8 a23 a9 a22 aen a11 b13 b14 d8 a9 d1 a8 d2 a7 d3 a6 d4 a5 d5 a4 d6 a3 d7 a2 reset c1 +5 +5 +1 f intrpt xtl1 xtl2 ua0 ua1 ua2 ua3 ud0 ud1 ud2 ud3 ud4 ud5 ud6 ud7 vref spkr txa2 txa1 rxa rxd txd stndaln iset gnd vdd rst x1 25 24 39 38 37 12 6 14 7 c13 j4 u4 a +5v 14 7 b ls04 com1 com2 8 5 4 3 2 11 1 12 23 1 36 35 27 28 29 30 31 32 33 34 19 0.1 f c6 35 17 4 3 16 18 8 r2 d1 c11 c11 t1 r1 600 3.9v 3.9v u5 lm386 220 f c14 no k1 d2 in4004 in4708 u8 4n35 d5 in4004 0.022 f midcom 671-8005 r5 1 fuseable a t r a1 a t r a1 r6 1 fuseable 0.22 f 250 vdc mov1 v250la20a r7 22 k +5 +5 +5 + r9 r4 10 5 8 0.047 c10 c9 0.1 f r3 5.1k 0.001 c12 0.1 f 6 3 7 4 spkr 2 22 k 11 2 14 13 22 6 7 15 9 20 40 r8 3 c4 0.1 f +5 +5 5 39 pf 11.0592 mhz 18 pf c2 figure 9: 73k222au typical integral application single-port mode
73k222au single-chip modem with uart 38 pc bus u2 u1 73k222au 8053 line phone irq3 irq4 a0 a31 b25 b24 b3 b1 a1 a30 a2 a29 a3 a28 a4 a27 a5 a26 a6 a25 a7 a24 a8 a23 a9 a22 aen a11 b13 b14 d8 a9 d1 a8 d2 a7 d3 a6 d4 a5 d5 a4 d6 a3 d7 a2 reset b2 10 f com 2 int com 1 int c1 +5v c3 j3 +5 +1 f intrpt xtl1 xtl2 ua0 rxd txd p1.0 p1.1 p1.3 p1.4 p1.7 p1.6 p1.5 x1 x2 ua1 ua2 ud0 ud1 ud2 ud3 ud4 ud5 ud6 ud7 vref spkr txa2 txa1 rxa ma2 int prst dclk data rxd rst p2 p0 p3.7 p3.6 p3.5 p3.4 ale vss vdd txd stndaln iset gnd vdd rst x1 25 24 39 38 37 6 14 7 c13 j4 u4 a c d +5v 14 7 b ls04 u4 ls04 u4 ls04 com1 com2 8 5 4 3 2 11 1 12 23 1 36 35 27 28 29 30 31 32 33 34 19 0.1 f c6 10 17 4 3 16 18 r2 d1 c11 c11 t1 r1 600 3.9v 3.9v u5 lm386 220 f c14 no k1 d2 in4004 in4708 u8 4n35 d5 in4004 0.022 f midcom 671-8005 fuse f1 j1 a t r a1 a t r a1 0.22 f 250 vdc mov1 v250la20a r7 22 k +5 +5 +5 + r9 r4 10 5 8 0.047 c10 c9 0.1 f r3 5.1k 0.001 c12 0.1 f 6 3 7 4 spkr 2 22 k 12 ma1 13 ma0 14 21 26 23 11 22 6 2 8 9 710 11 1 2 4 5 8 7 6 19 n/c 18 12 15 40 20 29 31 30 14 s1-1 s1-2 s1-3 s1-4 n/c n/c unused ports 15 16 17 13 8 lines 8 lines 9 20 40 r7 3 c4 c8 0.1 f 1 f +5 +5 + +5 5 39 pf 11.0592 mhz 18 pf c2 u3 ls30 figure 10: 73k222au typical integral application dual-port mode
73k222au single-chip modem with uart 39 mechanical specifications 40-pin dip 44-pin plcc pin no. 1 ident. 0.695 (17.655) 0.685 (17.399) 0.695 (17.655) 0.685 (17.399) 0.656 (16.662) 0.650 (16.510) 0.656 (16.662) 0.650 (16.510) 0.075 (1.905) 0.065 (1.651) 0.045 (1.140) 0.020 (0.508) 0.050 (1.270) 0.016 (0.406) 0.020 (0.508) 0.590 (14.986) 0.630 (16.002) 0.165 (4.191) 0.200 (5.080)
73k222au single-chip modem with uart 40 package pin designations (top view) caution: use handling procedures necessary for a static sensitive component. 600-mil 44-pin 40-pin dip plcc 73K222AU-IP 73k222au-ih ordering information part description order number packaging mark 73k222au 40-pin plastic dual in-line 73K222AU-IP 73K222AU-IP 44-pin plastic leaded chip carrier 73k222au-ih 73k222au-ih no responsibility is assumed by tdk semiconductor corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. no license is granted under any patents, patent rights or trademarks o f tdk semiconductor corporation, and the company reserves the right to make changes in specifications at any time without notice. acc ordingly, the reader is cautioned to verify that the data sheet is current before placing orders. tdk semiconductor corporation, 2642 michelle drive, tustin, ca 92780-7019, (714) 508-8800, fax: (714) 508-8877 ? tdk semiconductor corporation 04/24/00- rev.d ( ) / intrpt txa1 txa2 intrpt rxd txd ( ) prst iset reset ( ) / dclk (ua3) / ma2 ( ) / ma1 ( ) / ma0 stndln rxa spkr vref gnd 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 clk data / ( ) / ( ) xtl2 xtl1 / (n/c) ud0 ud1 ud2 ud3 ud4 ud5 ud6 ud7 ua2 ua1 ua0 vdd parentheses indicate single-port mode. 20 19 18 17 16 15 14 13 12 11 10 9 7 8 7 6 5 4 3 2 1 rxd txd ( ) / prst iset reset ( ) / dclk ( ) / ma2 ( ) / ma1 (cts) / ma0 stndln rxa spkr gnd clk (dtr) / data ( ) / xtl2 xtl1 n/c ud0 ud1 ud2 ud3 ud4 ud5 ud6 ud7 n/c ua2 ua1 ua0 vdd n/c / ( ) txa1 txa2 n/c 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6

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